The output signal from a standard memory cell provides a well defined predetermined voltage difference for both logical states which can be sensed by a standard sense amplifier. A gain memory cell differs from the standard memory cell by not having a well defined voltage difference for both logic states. The gain memory cell will deliver charge only when a logical "1" is present. The output signal from a gain memory cell cannot be sensed by a standard sense amplifier. The sense amplifier for a gain memory cell must provide a well defined output state for both logical levels "1" and "0" from a charge signal delivered only when a logical "1" is present.
In designing a sense amplifier, the potential for low-power operation is one of the attractive attributes of CMOS technology. A typical CMOS circuit application can provide very low standby power. Current flows in the circuit only when a transition of state is occurring. This feature makes it extremely easy to manage the power dissipation in CMOS designs. For an n-channel device the current carriers are electrons, whereas for a p-channel device the carriers are holes. Four separate regions or terminals exist in a MOS transistor: source, drain, gate, and substrate. For normal operation, the source, drain, and gate voltages measured with respect to substrate are positive for an n-channel device and negative for a p-channel device. The output is always connected to one of the power supply rails because at any given state only one transistor is on and the other is off. This guarantees that the logic swing will be determined by the power supply voltage only, and not by the ratio of the effective impedance of the devices, as is the case with static nMOS design.
The prior art is replete with sense amplifiers for use with memory cells. Some examples of prior art devices are as follows:
U.S. Pat. No. 3,932,848, entitled Feedback Circuit For Allowing Rapid Charging And Discharging Of A Sense Node In A Static Memory, issued to E. Porat, discloses an n-channel sense amplifier which incorporates feedback to a charged sense node. This allows for the rapid charging and discharging necessary to maintain a predetermined signal level. The sense amplifier uses a feedback circuit to control the potential drop of the bit line.
U.S. Pat. No. 4,434,381, entitled Sense Amplifiers, issued to R. G. Stewart, discloses a sense amplifier and concepts related to precharging and setting of sensing transitions. This circuit requires the use of a relatively high number of devices.
U.S. Pat. No. 4,567,387, entitled Linear Sense Amplifier, issued to I. T. Wacyk, discloses a sense amplifier that adds a bias current to the current delivered by the memory device.
U.S. Pat. No. 4,574,365, entitled Shared Access Lines Memory Cells, issued to R. E. Scheuerlein, discloses shared sense amplifiers for coupled memory cells. The memory cells are read out using a sense line, a first and a second bit line.
U.S. Pat. No. 4,970,689, entitled Charge Amplifying Trench Memory Cell, issued to Donald M. Kenney on Nov. 13, 1990, discloses a memory cell with a storage node that is not directly connected to the bit line during a read. The circuit requires two data lines for writing and reading.
U.S. Pat. No. 5,015,890, entitled Sense Amplifier Having Pull-up Circuit Controlled By Feedback, issued to Hiroaki Murakami et al. on May 14, 1991, discloses a sense amplifier for a low signal generated by a conventional memory cell.
U.S. Pat. No. 5,015,891, entitled Output Feedback Control Circuit For Integrated Circuit Device, issued to Yun-ho Choi on May 14, 1991, discloses a sense amplifier consisting of a read driver and an output latch transition block which utilizes a high device count.
U.S. Pat. No. 5,138,198, entitled Integrated Programmable Logic Device With Control Circuit To Power Down Unused Sense Amplifiers, issued to Ju Shen et al. on Aug. 11, 1992, discloses a logic device which powers down sense amplifiers that are not in use.
A problem typically associated with a sense amplifier for a gain memory cell is that of a relatively high component count. The high component count inflicts a cost and size penalty in the memory circuit and thus limits the operating speed and the density of the memory circuit.
It is, therefore, desirable to reduce the component count for a sense amplifier for a gain memory cell.
Another problem with sense amplifiers for gain memory cells is their power consumption both in the active mode and in the stand by mode. This power consumption limits the memory circuit density because of heat dissipation limitations as well as increases the power supply capacity requirements. It is desirable to minimize the power consumption of a sense amplifier for a gain memory cell in both the active mode and the stand by mode of operation.
It is, therefore, an object of the present invention to provide a sense amplifier which reduces power consumption.
It is a further object of the present invention to provide a sense amplifier capable of very fast sensing of the output signals of gain memory cells.